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Lalit Prasad Peri

**Architecture Performance Embedded Systems Innovation**

πŸ“« Email: lalitprasad@vt.edu
πŸ“ž Phone: +1 (540) 230-3095
πŸ”— LinkedIn: linkedin.com/in/lalit-p-31aa3025
πŸ›  GitHub: github.com/lalitprasadperi


πŸ” Professional Summary

Senior architect with 14+ years of cross-functional experience in CPU architecture, ASIC development, and performance engineering across industry-leading organizations including Qualcomm, ARM, and Samsung. Specialized in:


πŸŽ“ Education

M.S. in Computer Engineering
Virginia Tech, Blacksburg, VA, USA
Aug 2023 – May 2025 (GPA: 3.50/4.00)
Thesis: Novel RISC-V CPU architecture for memory security and performance use-cases, with custom ISA and LLVM compiler extensions.

B.Tech in Information Technology
National Institute of Technology, Bhopal, India
2004 – 2008


πŸ’Ό Work Experience

Senior Staff, Performance Architecture

Qualcomm, Bangalore, India
Dec 2021 – May 2023

Staff CPU Architect – Performance & Workloads

ARM, Bangalore, India
Jul 2019 – Oct 2021

Consultant, ASIC Design

ALTEN, Lund, Sweden
Mar 2018 – Jun 2019

Lead Design Engineer

NXP Semiconductors, Noida, India
Nov 2016 – Feb 2018

Lead Design Engineer

Freescale Semiconductors, Noida, India
Aug 2011 – Nov 2016

Senior Project Engineer

Wipro Technologies, Bangalore, India
Jun 2008 – Aug 2011


πŸ’‘ Internship (Summer 2024)

Samsung, Austin, TX


🧠 Technical Skills

Architecture & Modeling: gem5, SystemC, QEMU, Simpoints
Performance Benchmarks: SPEC2k6/2k17, Geekbench v5/v6, Speedometer2.0, SPECjBB
Programming: C, C++, Python, Perl, Bash
RTL Design: Verilog, SystemVerilog, FPGA prototyping
Verification & Emulation: UVM, SVA/PSL, Cadence Palladium, Veloce
Compiler & ISA: LLVM, custom ISA (ARM, RISC-V)
Tools & Scripting: Git, Make, TCL, MATLAB


πŸ§ͺ Projects & Research


πŸ“œ Publications & Contributions

(Include specific papers, patents, or conference presentations if applicable. Placeholder for now.)


🌐 Portfolio & Contact

For source code, technical blog posts, and demos, please visit:
πŸ”— github.com/lalitprasadperi


This resume is hosted on GitHub Pages. Last updated: July 2025