Lalit Prasad Peri
**Architecture | Performance | Embedded Systems | Innovation** |
π« Email: lalitprasad@vt.edu
π Phone: +1 (540) 230-3095
π LinkedIn: linkedin.com/in/lalit-p-31aa3025
π GitHub: github.com/lalitprasadperi
π Professional Summary
Senior architect with 14+ years of cross-functional experience in CPU architecture, ASIC development, and performance engineering across industry-leading organizations including Qualcomm, ARM, and Samsung. Specialized in:
- CPU Microarchitecture Design & Modeling
- Compiler & ISA Extensions (LLVM, RISC-V, ARM)
- Workload Analysis & Performance Benchmarking
- RTL Design & Verification (ASIC, FPGA)
- Pre/Post-Silicon Validation and Emulation
π Education
M.S. in Computer Engineering
Virginia Tech, Blacksburg, VA, USA
Aug 2023 β May 2025 (GPA: 3.50/4.00)
Thesis: Novel RISC-V CPU architecture for memory security and performance use-cases, with custom ISA and LLVM compiler extensions.
B.Tech in Information Technology
National Institute of Technology, Bhopal, India
2004 β 2008
πΌ Work Experience
Senior Staff, Performance Architecture
Qualcomm, Bangalore, India
Dec 2021 β May 2023
- Led pre/post-silicon evaluation for custom Arm CPU cores using SPEC2k17, Geekbench v5, Speedometer2.0.
- Worked on ASIC architecture modeling, power/performance analysis, and custom SoC development.
- Focus on innovations in CHI interconnect, LLC, and memory controller concurrency across CPU, GPU, and NSP.
Staff CPU Architect β Performance & Workloads
ARM, Bangalore, India
Jul 2019 β Oct 2021
- Modeled custom ARMv8/v9 ISA extensions for warehouse-scale computing, achieving notable performance gains.
- Contributed to scalable matrix extensions (SME) for ARMv9 CPUs, targeting ML and DSP applications.
- Led end-to-end full-stack analysis from application to microarchitecture using Speedometer and Geekbench.
Consultant, ASIC Design
ALTEN, Lund, Sweden
Mar 2018 β Jun 2019
Lead Design Engineer
NXP Semiconductors, Noida, India
Nov 2016 β Feb 2018
Lead Design Engineer
Freescale Semiconductors, Noida, India
Aug 2011 β Nov 2016
Senior Project Engineer
Wipro Technologies, Bangalore, India
Jun 2008 β Aug 2011
π‘ Internship (Summer 2024)
Samsung, Austin, TX
- ASIC RTL integration, subsystem development, and integration methodology improvement.
- Modeled performance bottlenecks in multi-level cache architectures in LTE PHY ASICs.
- Benchmarked Cortex A72-based networking ASIC for cache/interconnect optimization.
π§ Technical Skills
Architecture & Modeling: gem5, SystemC, QEMU, Simpoints
Performance Benchmarks: SPEC2k6/2k17, Geekbench v5/v6, Speedometer2.0, SPECjBB
Programming: C, C++, Python, Perl, Bash
RTL Design: Verilog, SystemVerilog, FPGA prototyping
Verification & Emulation: UVM, SVA/PSL, Cadence Palladium, Veloce
Compiler & ISA: LLVM, custom ISA (ARM, RISC-V)
Tools & Scripting: Git, Make, TCL, MATLAB
π§ͺ Projects & Research
- RISC-V CPU with Memory Security ISA β Designed custom ISA extensions and LLVM passes for security and performance.
- CHI QoS Modeling β Innovations in cache-coherent interconnect for heterogeneous concurrency.
- ISA Customization for Warehouse Computing β ARMv9 ISA prototyping for large-scale apps.
- Multi-core DSP Validation β FPGA-based early prototyping for baseband DSP systems.
π Publications & Contributions
(Include specific papers, patents, or conference presentations if applicable. Placeholder for now.)
- Placeholder: βOptimizing RISC-V Pipelines for Secure Memory Accessβ β Draft under review
- Placeholder: Contributor to custom LLVM passes and instruction selection
π Portfolio & Contact
For source code, technical blog posts, and demos, please visit:
π github.com/lalitprasadperi
This resume is hosted on GitHub Pages. Last updated: July 2025